ADC DAC and Back EMF loop control for the bass speaker

The ADDA Analog Input and Output board is the most complex design of the whole system.
It contains over 300 components and is double sided mounted on a four layer board.
The total schematic covers six sheets being:
- Top level sheet of the five pages with sheet interconnections
- The audio input section and ADC
- The loudspeaker Back EMF extraction and loop control of the bass speaker power amplifier.
- Mid and High DAC's, I/V conversion and analog filtering.
- Low DAC, I/V conversion and analog filtering.
- analog activity detect amplifier, master clock oscillator and the powersupplies

The audio input & ADC

The single ended analog audio input signal is first low pass filtered using a second order Butterworth low-pass filter in multiple feedback topology with its -3dB roll-off frequency at 50KHz. The fact that this is an inverting topology is simply corrected in the ADC phase splitter stage.
A Sallen & Key topology is often used but I prefer the Multiple Feedback type since it does not loose its low pass characteristic when the Gain Bandwidth Product of the opamp reaches 0dB.
I have used an OPA1611 (U200) in the filter stage for its verly low noise and superior sound quality.

The analog input is protected using a TPD2E007 suppressor to avoid any damages due to ElectroStatic Discharge when the speaker system is hooked up.
There is no input signal capacitor present but a servo amplifier like in the Power Amplifier holds the output of the filter  stage at zero DC level. As servo opamp an OPA140 (U202) is used. The pole of the servo amplifier lies at 0.6Hz.
The actual high pass filtering to protect the speakers against too low frequencies is done in the Digital Signal Processor TAS3208.
The servo topology compensates for the DC offset and drift of the filter opamp but also for any DC level on the input up to 8V DC.

The phase splitter stage is built with a dual version of the OPA1611, the OPA1612 (U204) for the same reasons:low noise and quality.
The bias voltage "Vcom" that is generated by the PCM1804 ADC (U205) is buffered using an OPA140 (U203) and fed to the offset inputs of the phase splitter opamps.
All opamp powersupplies are decoupled with 22uF electrolytic through hole caps and bypassed with 100nF X7R ceramic caps. 
All connections from the top side to the bottom layer ground plane are done with minimum 2 vias.
  
The PCM1804 (U205) operates in 48KHz, 24bit I2S master mode and generates the I2C signals for the DACs, the Digital Signal Processor TAS3208 and the piggyback connector. This connector was added for future addition of a digital (AES/EBU) audio input. The low jitter masterclock that generates the SCLK for the PCM1804 is discussed in the last sheet.


A strap option is provided to use the PCM1804 digital high pass filtering, which I enabled.
Carefull PCB layout has been used to place all decoupling capacitors (47uF electrolytics in parallel with 100nF X7R ceramics) as close to the PCM1804 as possible and connect directly to the groundplane beneath the device at the top side of the PCB. There are 12 vias to connect that topside groundplane with the bottom side groundplane.

Only the left audio channel of the PCM1804 is used and its clip output is isolated by an opto coupler.
This signal is ORed with other clip signals from the low, mid and high amplifiers and drive a clip indicator LED mounted behind the front of the speaker cabinet.
The SCLK, BCLK, LRCLK and DATA output signals are transported to the TAS3208 EVM via a 10cm flatcable.
 
Two CDCLVC1104 low jitter 1:4 clock splitters are used (U206 and U207) to distribute the I2S signals BCLK and LRCLK to the DACs, the digital audio processor and a digital audio input piggyback connector.

Speaker BEMF & loop.

The bass speaker back EMF extraction is done by placing the speaker in a bridge topology with a 0.34Ohm power resistor in series in one branch and a higher impedance second branch with a potmeter (P300) to adjust the bridge balance.
This is not a DC balance but an impedance balance and is used to tune the loop for a stable operation at the highest possible compensation.
U300 is a TPD2E007 protection device to avoid blowing out the bridge amplifier due to ESD.
Make sure to turn the bridge balance potmeter P300 in its lowest position to avoid the poweramp to clip at turn on.
Experiments showed that an OPA134 opamp (U300) works best in this topology as difference amplifier with a gain of 0dB.
With some speakers a small RC compensation in parallel with the opamp feedback resistor is needed to compensate for the inductance of the speaker and to keep the loop stable once adjusted.
The Seas Design L26ROY has a very low inductance and compensation was not nessesary.

The output of the bridge amplifier delivers the Back EMF signal that represents the voice coil speed.
Voice coil speed is not nessesarely the same as the conus speed due to all sorts of mechanical imperfections over frequency like conus breakup. That is the reason I chose for a relative heavy aluminium bass speaker with a rigid connected voicecoil. The drawback is a much higher mass that impacts the highest frequencies a servo feedback system can produce.
 

What we intend to keep constant over frequency is Sound Pressure Level (SPL) that equates to the conus acceleration. Since the back EMF represents the the voice coil speed and we want to control the acceleration there are two options to close the feedback loop of the Back EMF circuit with the input signal.
The input signal of the amplifier represents the speaker accelleration and thus the sound pressure if we ignore the cone diameter dependency.
If we integrate the input signal to get conus speed the back EMF signal can be summed to the integrated input signal to close the feedback loop.
If we differentiate the back EMF signal to get the Back EMF as acceleration information it can be summed directly to the input signal.

There are pro's and con's to either aproach.
A differentiator in the Back EMF loop path will add 90 degrees of phase shift and decreases the phase margin to a quarter if we want a minimal 45 degree phase margin. The advantage is that there are no DC offset issues with the high gain of the feedback loop.
I have chosen for the integrator in the input path to maximize the phase margin to tune the system as close to instability as possible, creating a tighter control. This comes with a drawback in the form of DC offset. An "ideal" integrator has open loop gain at DC.
The gain of integrator U302A has been limited for DC to 20dB and the AC gain is 0dB at 19Hz.
The servo amplifier in the poweramp is taking care of the small DC offsets caused by the integrator.

The one thing to be carefull about is to have no audio signal present when the system starts up.

Since the system starts on an audio detect, e.g. audio present, this audio signal has to be blocked from the Servo Amplifier as long as the output relay of the power amplifier is open. With the speaker disconnected the total loop gain of the system equals the gains of integrator, summing-amp and power-amp equal to 0dB+32dB+29dB=61dB. This high gain causes a small input signal to clip the power amplifier.

This was insight that came after the design of the ADDA board. For that reason I added a small circuit that blocks the audio signal from entering the servo loop until the PWROK signal activates the power amplifier output relais plus a 500mS delay. When PWROK de-activates it immediately disconnects the autio input signal to the servo amplifier. 

I used the piggyback connector J128 to power the circuit and get the PWROK signal that controls the passing of the audio signal only after the power amplifier output relais has been activated.

The circuit diagram is added to the bottom of this page. 

Once the relay and thus the feedback loop is closed the overall gain drops to ~28dB, dependent how the closed loop gain is adjusted with potmeter P301.

The way to adjust the Back EMF is to rotate P301 to lowest gain, P300 to its lowest position.
Turn up P300 until the system starts oscillating. Turn the pot back two turns for stable operation and turn up P301 for the desired system gain.
I calculated the system gain for 29dB (28x) to avoid power amp clipping before ADC / DAC clipping having a maximal input signal of 875mV eff.

Before designing the ADDA board I built a test setup for the BEMF circuit using a dual sine burst signal of 40Hz with an interval of 150mS to test the impulse response of the system.

The servo bass speaker frequency graph can be found in the DSP secion. The acoustic impulse response is shown below.  This graph was measured with a microphone close at the bass speaker conus.You can see a small overshoot at the end of the burst but overall the response is very clean and damped. The frequency response is a straight line from 20Hz to 150Hz. Above 150Hz the mass of the speaker kicks in. This behaviour is reflected by a controlled bass experience that is as much felt as heared.

Low, Mid and High DAC's

For the DAC's the PCM1794 (U400A and U503A) was selected, one of the best DACs on the market which has a differential current output.
The 48KHz, 24bit I2S signals BCLK and LRCLK come via the clock splitters from the ADC (PCM1804), the SCLK comes from the clock splitted master oscillator, the data comes from the Digital Audio Processing board, TAS3208.
A low noise dual opamp, the OPA1612 (U401 and U500) performs the differential I-to-V conversion and a second OPA1612 (U402, U404 and U501) do the differential to single ended conversion and the low-pass filtering.
The low-pass filters are exactly the same as the analog input filter, a second order Butterworth in multiple feedback topology with its -3dB frequency at 50KHz.
At the outputs potmeters are placed to adjust the analog input levels for the low mid and high power amplifiers.
This could easily have been done in the TAS3208 but I wanted to maintain maximum digital resolution.
On drawing 6 is also the master reset circuit located that is built up with an RC and a Schmittrigger input logic gate.

Clock oscillator & power

The last sheet contains the powersupplies, +/-12V for the opamps that come from the PAAS module and that are low-pass filtered with 10uH inductors and 100uF caps.
The 5V and 3V3 supplies are derived from the 5V5 PAAS supply using low noise fixed output voltage LDO's TPS79650 (U604) and TPC79633 (U605)
There is a separate low noise TPS79133 LDO (U607) to power the low jitter 12.288MHz Tentlabs oscillator circuit (U602).    http://www.tentlabs.com/Components/XO/index.html

The additional inductor in the powerline of the oscillator was included with the oscillator and provides additional high frequency filtering.
The masterclock is distributed with the CDCLVC1106 (U603) with 6 buffered outputs of which 5 are used to drive the ADC, two DACs, the TAS3208 and the piggyback connector.

After testing the audio detect circuit on the Inrush Current Controller board (ICC) it shows that the high gain and rectification disturbed the audio signal going to the ADDA board.
The +3V3 always ON is used to drive a switch cap inverter, the TPS60403 (U606) that creates the -3V3. This dual supply is the always ON supply for the OPA140 (U600) in a x3 gain inverting topology to isolate the audio input signal for the audio ICC audio detector.

The total design as said contains over 300 components and was fitted on a 10cm x 8cm four layer PCB, with all SMD components at the top side plus the potmeters, oscillator, power resistors for the BEMF bridge and two filter caps.  All electrolytic decoupling caps were located at the bottom side.
Bottom side is the groundplane, topside is the signal layer with as much groundcopper as possible, especially under the converters where analog and digital grounds are connected.
Two mid layers carry the powersupply signals: the +/-12V, 5V and 3V3 supplies for the converters.

For the pad to plane connections I used crosshairs in the PCB layout. For a next design I will use massive connections. Especially with the ground plane this was a source of additional 50Hz related noise that I had to correct manually to bring the noise to an acceptable level (-100dB).
The groundplane is also the master summingpoint for the low power analog signals of all PCB's.

 

Below the Servo Disconnect schematic as discussed under the BEMF servo loop.