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# Phono Amplifier (Updated march 2018)

Before committing anything to a PCB layout I decided to simulate and breadboard different Phono amplifier circuits.

To verify a Phono amplifier circuit ‘s stability I used a simulation technique described in a series of 15 papers called **"Tricks for Stability" by Tim Green****.**

I recommend to download and read these articles, at least items 1-3.

Fig.1 represents the Opamp Loop-Gain Model.

AoL is the Open Loop Gain, B is the Feedback Factor(Vfb/Vout), Vin is the input Voltage and Vout is the Output Voltage.

The Closed Loop Gain = Vout/Vin = AcL = AoL/(1+AoLB), where AolB is the loop gain.

If AoL is high then AcL ~ 1/B.

From the equation Vout/Vin = AoL/(1+AoLB) follows that if AoLB = -1, Vout/Vin = AoL/0 = infinite -> oscillation!

AoLB is the gain left to correct for errors in the Vout/Vin or closed loop response.

If AoLB = -1, it means a phase shift of +/- 180deg. at a gain of 1 (0dB)

The frequency where the open loop gain AoL intersects with 1/B we call Fcl.

The stability criterium is then:

At Fcl, where AolB = 1(0dB), the phase shift must be < +/-180deg.

A desired phase margin (distance from +/-180-deg.Phase shift) is >45deg.

I want to check the magnitude and phase of the loop gain AoLB of the Phono amplifier circuit to verify stability.

This can be done with a Spice simulator by breaking the feedback loop open and inject a small AC signal in the loop as described in the Tim Green articles.

As Spice simulator I use TinaTI, a free download Spice simulator from the Texas Instruments website.

Fig.2 shows how the Phono amplifier simulation schematic looks like in TinaTI with broken feedback loop.

The +input is grounded. The output is disconnected for AC but to allow the Spice simulation to work there has to be a DC connection. This is done by the 1GH inductor, A value that is only possible in simulations.

The injected AC voltage must have an infinite impedance for DC: the 1GH capacitor.

What we want to see plotted are AoL (Open loop Gain) and the Loop Gain or 1/B.

Looking at nodes N1, N2 and N3 in Fig.2, the AoL=N2/N1 and 1/B=N3/N1.

Tina produces the required amplitude and phase plots of N1, N2 and N3.

By post processing the plots AoL and 1/B are derived according to the formulas above (AoL=.N2/N1, 1/B = N3/N1)

A first indication whether a circuit is stable or not is the "rate of closure" between the AoL and 1/B gain curves. The point where they intersect is at frequency Fcl.

In the frequency-amplitude plot a horizontal line indicates that no pole or zero is present at those frequencies.

A 6dB/octave or 20dB/decade decreasing curve indicates a single pole, a 40dB/decade decreasing curve indicates a second pole. Inversely does a 20dB/decade increasing curve indicate a zero and a 40dB/decade increase a second zero.

If the AoL and 1/B curves intersect with a 20dB/decade angle it indicates a stable circuit. If that angle is from a higher order it means the circuit is unstable.

The phase margin at Fcl (AoL = 0dB) can be derived from the AoL and 1/B phase plot.

The 3dB point of a pole or zero can be identified by a 45deg. change in phase on the phase plot.

My first simulation test was to see if an opamp like the OPA134 would be stable with an active RIAA feedback network .

The plot in Fig.3 shows the datasheet AoL and Phase plot of the OPA134. Fig. 4 shows the simulated AoL (red) and Loop Gain(brown) curves, the top plot is amplitude, the bottom plot is phase. The simulated AoL plot fit nicely with the OPA134 datasheet plot.

As with many opamps is the first and dominant pole below 10Hz. The AoL gain starts at ~130dB and decreases at the dominant pole with 20dB/decade rate towards Fcs. Before it reaches Fcs a second pole starts to influence the AoL curve but its -3dB point (45deg. phase shift) is just before the AoL 0dB point.

The point where the red AoL curve hits the 0dB gain line is just below 10MHz, where the phase margin is still >45deg.

The angle of closure between the AoL and 1/B curves is a first order (20dB/decade) so this Phonoamp circuit is likely to be stable.

The next step was to measure the output noise of this Phono amplifier circuit to see if such a simple circuit would be sufficient for a high quality Phono amplifier.

Fig.5 shows the simulated AcL (Closed Loop) amplitude and Phase plot, with a gain at 1KHz of 34.4dB. The curve follows the RIAA recommendations.

For noise and distortion I tend to rely on actual hardware measurements rather than simulation.

I built a breadboard and placed it in a metal lunchbox with connections for the power supplies, inputs and outputs.

When dealing with circuits at such low voltages shielding is the way to go to get reliable measurement results.

I tested three different opamps, the NE5534, the OPA134 and the OPA1641. The first one is a bi-polar opamp, the two others are JFET input opamps.

I used a sinewave signal source with an internal impedance of 3KOhms to aproach the internal impedance of an average Moving Magnet Phono cartridge.

There was a noticable output DC offset difference between the NE5534 and the two other opamps.

This makes sense since both inputs of the opamps are loaded with very different impedances (100Ohms on the - input, 3KOhms at the + input). A bipolar opamp with its inherent larger base currents will translate that in a higher output offset voltage.

All three opamps gave comparable output noise levels of 0.7mVeff.

Applying a 1KHz sinewave of 19mVeff. gave a 1Veff. output signal and yields a SNR of 71dB.

That is not bad but not great either since I aim for at least 90dB SNR for my Phono amplifier.

A different aproach is asked for.

The first stage of an amplifier greatly determins its overall noise level. It is therefore important to aim for the lowest noise input stage.

Many designers favour BJT's over FET's when it comes to low noise input stages but the advantage of using a JFET input stage is that with the high impedance of MM cartridges current noise plays an important role which JFET inputs handle better than BJT inputs.

If you know what the shortcomings of JFET's are, you can adapt the design into an equally or in my opinion better amplifier with JFETs than with BJT's.

In my Denon pre amplifier Toshiba JFET's type 2SK369 are used. Their datasheet indicates that they are designed for low noise audio applications and have a typical noise figure of 1dB.

I decided to put a differential pair of 2SK369 JFET's in front of an OPA134 opamp to see how that would improve the overal noise.

I found a Spice model of the 2SK369, that I entered in the TinaTI "Noname" JFET model. The Spice model is limited but seems sufficient for AoL measurements. I measured a number of 2SK369 FET's and their gain and bandwidth results line up with the Spice simulations. Noise and distortion will have to be be measured on actual hardware.

The Simulation schematic of the Opamp with discrete JFET input stage is shown in Fig6.

The resulting AoL and 1/B plots can be seen in Fig.7.

The AoL goes up to 160dB but the dominant pole is still determined by the OPA134 and stays at 2Hz. The second pole at 10MHz also remains but now at an AoL of 42dB which pushes the AoL 0dB point out to 30MHz.

The "rate of closure" of the AoL and 1/B is now 40dB/decade.

This means that this circuit is not stable for a RIAA-Phono amplifier.

This is one of the pittfalls for RIAA Phono amplifiers. Fcl (or the "rate of closure" point of AoL and 1/B) falls at the same frequency as the AoL 0dB point since the RIAA feedback reduces the AcL to 0dB for higher frequencies.

A phono amplifier with a high AoL is likely to have its Fcl (intersection point of AoL and 1/B) above the second pole frequency of the AoL curve, hence a "rate of closure" higher than 20dB/decade resulting in instability and HF oscillation.

This is HF oscillation is exactly what I observed when I built this circuit on the breadboard.

A combination of an Opamp and a low noise JFET input stage will therefore not be easy to stabilize for a RIAA amplifier.

This conclusion led to my decision to build a 100% discrete RIAA Preamplifier using 2SK369 JFET's in the differential input stage.

Fig. 8 shows the simulation schematic of the input stage.

JFET's are known for their large variation in Vgs. The 2SK369 datasheet shows that Vgs min-max values are -0.3V to -1.2V; a factor of 4.

The differential JFET gates are biased to ground with a resistor, usually 47KOhms at the + input for a Moving Magnet cartridge and a much lower value at the - input (100Ohms or lower).

A resistor in the common source determines the drain current but with a variation in Vgs of a factor 4 the resistor value in the source will have to optimized for every individual setup.

A way to solve this is to use a current source in the JFET's common source to the negative power rail (T13, T14).

The JFET's set their Vgs automatically with a current source in the common source.

In a simulator are both JFET's perfectly matched but in real life this is not the case. The wide range of Vgs brings up another problem if you use a differential pair. If both JFETs of the differential pair have different Vgs voltages you are bound to have large DC offsets at the output of the amplifier.

More realistic: The output of a Phono amplifier with a DC gain of around 60dB will clamp to one of the supply rails.

So unless you are prepared to buy a large amount of JFET's and pair them on equal Vgs, a different solution has to be found.

I use a DC servo amplifier that biases the - input JFET to remove any DC offsets at the output of the Phono amplifier.

A second shortcoming of JFET's is their AC signal distortion due to variations in Vds, which happens if you apply an AC signal at the gate of the FET and subsequently Vds varies.

A way to reduce that distortion is to put a differential cascode BJT pair in the drains of the JFETs(T5 and T6). This stabilizes the Vds of the FETs and reduces the distortion in the input stage.

The third shortcoming is the low voltage gain of a JFET.

One solution to that is to increase the value of the drain resistors but that means a high supply voltage, something I do not want since I have a maximum +/-15V of power supply rails at my disposal.

One other solution is to put JFET's in parallel to increase the gain and keep the same value of drain resistors, which also helps to reduce the noise. 2 FET's in parallel gives 3dB and four FET's in parallel gives 6dB reduction in noise, at least in theory.

Another way to boost the voltage gain is to artificially increase the drain resistor impedance and place a current mirror (T1 and T2) in the differential input stage on top of the cascode BJT's. This also forces the drain currents to exact mirroring, which also reduces the distortion and lowers offset errors.

R1 and R2 (12Ohms) in the current mirror were added to compensate for Vbe differences in the current mirror BJT pair. Again not required for simulation but nessesary in real life.

Fig.8 shows the TinaTI schematic of the complete input stage with current source T13 and T14, cascode pair T5 and T6 and the current mirror formed by T1 and T2.

Simulation shows that this input stage has a gain of 64dB and the first pole lies around 120KHz. (Fig.9).

Without the current mirror and 330Ohm drain resistors the gain is 16dB with the first pole at 200KHz.

The rest of the amplifier circuit is reasonably straight forward (see Fig.10)

To avoid loading the differential input stage T3 was added. T4 is loaded on its collector with a second current source (T11 and T12) to boost the voltage gain. T7 and T8 form the complementary output pair.

Capacitor C2 determines the dominant pole of the amplifier. Fig. 11 shows the AoL , 1/B Gain and Phase curves of this amplifier.

The AoL is 130dB, with the dominant pole at 130Hz. The second pole is at 35MHz, almost at Fcl. The intersection of the AoL and 1/B curves is with 20dB/decade and 45deg. phase margin. This amplifier is stable and suited for RIAA correction.

Curious if the simulations would live up against the real thing I built this circuit and added the DC servo amplifier to avoid DC offsets at the output and put it to the test.

The circuit is stable, no signs of HF oscillations on the scope. I then performed the same measurement as the with the OPA134 Phono amplifier. 19mVeff. input sinewave at 1KHz, resulting in 1Veff. output signal. I measured an output noise of 18uV, that equates to a SNR of 94.9dB. THD at 1KHz came out at 0.004%.

I was happy with this result but is that the best possible? Maybe I am going over board here but knowing that parallel input stages further reduce noise I decided to put a full blown Phono amplifier circuit on the Preamp PCB.

There is a risk that the gain of a parallel differential FET input stage increases the AoL too much and causes the same stability issue as the OPA134 with the FET stage in front but I can easily take out FET's or remove the current mirror from the final PCB to get the design stable again.

I increased the number of differential JFET input pairs to four in parallel, each with their own current source and one common cascode stage and current mirror.

I reduced the current in each FET input stage current source to 2.5 mA, adding up to 10mA per amplifier input stage.

After my simulation and breadboarding experiments with the Phono amplifier I decided to build the power supply next.

More on the Power Supply design in the chapter "Power Supply".

Once the Pre amplifier PCB arrived from the PCB store (Euro Circuits) it took me 5 weekends to solder all components and the sixth weekend the big moment was there.

Turned out that my suspicion on too high AoL was justified. The Phono amplifier oscillated above 10MHz.

I modified the Phono amplifier Spice schematic and put four input stages in parallel (Fig.12) and ran the simulation to check what the problem was.

As can be seen in Fig.13 did the AoL increased from 130dB to 136dB. The second pole is at 29MHz, where the AoL is still at 6dB and flattens off. There is a third pole since the phase keeps dropping. The intersection of the AoL and 1/B curves is now at 92MHz. The angle of closure of AoL and 1/B seems like 20dB/decade but the phase at Fcs is already through 180deg. towards -70deg. so oscillation confirmed by simulation.

Since I was curious how much the four parallel input stages would reduce the SNR I decided to take out the current mirror. With the lower impedance in the drains of the input stage I will have to increase capacitor C2 that determines the dominant pole. Resistors R1 and R2, now the drain resistors were replaced by 330Ohm values.

The resulting simulation schematic is in Fig.14 and the AoL - 1/B plots are in Fig.15.

The AoL is reduced to 90dB but the intersection of the AoL and 1/B curves is again 20dB/Decade with a phase margin of 65deg. This circuit should be stable.

On my Pre amplifier PCB I removed the current mirror transistors and shorted the emitter and collector connections, increased C2 to 220pF, changed the drain resistors to 330Ohms and switched the power on.

This time the Phono amplifier was stable. I quickly measured the output voltage without any input signal at 9.6uV, which equates at 1Veff. to a SNR of 100.4dB!!!

That is 0.5dB less then expected. Probably due to the reduction in drain currents that increased the noise figure of the FET's.

The THD is much higher without the current mirror and more than 40dB lower AoL but still a decent 0.02%.

In the final hardware design I also added reed relays that switch in a 10Ohm feedback resistor to ground at the - inputs and a 110Ohm resistor to ground at the + inputs to accomodate Moving Coil cartridges. The output noise increases then to 95uV, which relates to a SNR of 80.4dB, not bad for a MC Phono amplifier.

Fig.16 shows the AoL and 1/B curves of the MC Phono amplifier with a 20dB higher AcL. Also here the intersection of AoL and 1/B are 20dB/decade and the phase margin at Fcl is >45deg.

That plot also shows the 20dB lower feedback margin, hence the importance of having an inherent low distortion design. Low distortion is realized by a good input stage design.

With this design I have demonstrated that a good Phono pre amplifier must have an open loop gain that is not too high to prevent the second pole causing instability problems but high enough AoL to support the high gain of MC Phono amplifier designs. Simulation is a good aid to verify if a design is stable but actual measurements will be the final proof whether a design is solid.

A third order Bessel 15Hz High-Pass filter is placed after the Phono pre amplifier to remove any rumble from non flat records.

The Phono amplifier schematics can be found in the "Preamp" section PDF's.

The measured RIAA curve table and deviations are shown below.